1. Field of the Invention
The present invention relates to electronic circuits, and more particularly to memory cells for storing digital information.
2. Description of Related Art
Semiconductor memories are vital components for mainframe and personal computers, telecommunications, automotive and consumer electronics, and commercial and military avionics systems. Semiconductor memories are characterized as volatile random access memories (RAMs) or nonvolatile devices. RAMs can either be static mode (SRAMs) where digital information is stored by setting the logic state of a bistable device, or dynamic mode (DRAMs) where digital information is stored through periodic charging of a capacitor.
SRAM is typically arranged as a matrix of memory cells fabricated in an integrated circuit chip, and address decoding functions in the chip allow access to each cell for read/write functions. SRAM memory cells use active feedback in the form of cross-coupled inverters to store a bit of information as a logical "0" or a logical "1". The active elements in the memory cells need a constant source of power to remain latched in the desired state. The memory cells are often arranged in rows so that blocks of data such as words or bytes can be written or read simultaneously. Address multiplexing is used to reduce the number of input and output pins. SRAMs have undergone dramatic increases in density. For instance, 16 megabit SRAMs have been developed with 0.4 micron CMOS technology. SRAM memory cells have many variations. The basic CMOS SRAM cell consists of two transistors and two load elements in a cross-coupled inverter configuration, with two select transistors added to make up a six-transistor cell. Polysilicon load resistors have been used instead of PMOS transistors to reduce cell size. Furthermore, there are application-specific variations of the basic SRAM cell. Application-specific SRAMs include extra logic circuitry to make them compatible for a specific task. For instance, an eight-transistor, double-ended, dual-port cell can be accessed through both ports and is useful in cache architectures embedded in memory of a microprocessor. A ninetransistor content-addressable memory (CAM) cell is used in applications where both the contents and location of the cell must be known.
FIG. 1 is a circuit diagram of a conventional application-specific SRAM memory cell. Memory cell 10 includes cross-coupled inverters 12 and 14, inverters 16 and 18, N-channel MOS transistors 20, 22 and 24, and P-channel MOS transistor 26. Write data line 30 applies a write data (WD) signal to the drain of transistor 20, write address line 32 applies a write address (WA) signal to the gate of transistor 20, clock line 34 applies a clock (CLK) to the gate of transistor 22, read address line 36 applies a read address (RA) signal to the gate of transistor 24 and to inverter 18, and read data line 38 outputs a read data (RD) signal. The write data signal provides a bit of information to be written into memory cell 10, the write address signal selects memory cell 10 for a write operation, the clock provides timing synchonization for the write operation, and the read address signal selects memory cell 10 for a read operation in which the stored bit is provided as the read data signal.
During a write operation, initially the write data signal assumes a logical value and the write address signal is high to select memory cell 10. Thereafter, the clock goes high, the write data signal and the write address signal remain stable while the clock is high, and transistors 20 and 22 couple the write data signal to node 40. The write data signal determines the logical value of node 40. If the write data signal and node 40 have identical logical values then node 40 retains this logical value. Alternatively, if the write data signal and node 40 have different logical values then the write data signal changes the logical value of node 40, and inverter 12 changes the logical value of node 42. Thereafter, the clock goes low, and inverter 14 functions as a "keeper" to prevent node 40 from drifting to another logical value. Accordingly, inverters 40 and 42 latch the write data signal and store a bit of information at node 40 with the same logical value as the write data signal. In addition, inverter 12 provides a complement of the bit at node 42, and inverter 16 provides a double complement of the bit, which is equivalent to the bit, at node 44. Thus, nodes 40 and 44 have identical logical values. In addition, inverter 16 provides a buffer to protect nodes 40 and 42 from the read operation.
During a read operation, the read data signal goes high to select memory cell 10. Transistors 24 and 26 in combination with inverter 18 provide a transmission gate that opens when the read data signal is high and closes when the read data signal is low. Accordingly, when the read address signal is high, transistors 24 and 26 couple node 44 to read data line 38 to provide the read data signal with the same logical value as the stored bit. Although transistor 24 alone could provide a switch for coupling read data line 38 to node 44 in response to the read address signal, this would introduce a threshold voltage (V.sub.TN) drop between read data line 38 and node 44 when the stored bit has a high logical value.
Memory cell 10 is particularly well-suited for providing a flexible building block for a large memory array. For instance, memory cell 10 can receive multiple read address lines for driving multiple read data lines by replicating the combination of inverter 18 and transistors 24 and 26. Unfortunately, memory cell 10 has several drawbacks.
Memory cell 10 includes a critical speed path between write data line 30 and node 40 during write operations. When the write data signal is high and node 40 is low, transistor 20 introduces a threshold voltage (V.sub.TN) drop between write data line 30 and node 40 which increases the time needed for the voltage at node 40 to reach the trip point of inverter 12. Increasing the sizes of transistors 20 and 22 increases their drive currents and therefore increases the rate at which node 40 charges, however this approach also increases the loading for write address line 32 and clock line 34, thereby causing other time delays, and requires more surface area. Furthermore, as the supply voltage decreases, the write data signal requires even more time to charge node 40.
Memory cell 10 also includes a critical speed path between read address line 36 and read data line 38 during read operations. Read address line 36 is coupled to transistor 24 and inverter 18, which includes an N-channel transistor and a P-channel transistor (not shown). These three transistors each increase the loading for read address line 36, thereby increasing time delays. In addition, since P-channel transistors tend to be slower than N-channel transistors (due to the greater mobility of electrons than holes), it is often undesirable to place a P-channel transistor in the critical speed path. Inverter 18 and transistor 26 are not essential, however, as mentioned above, they prevent a threshold voltage (V.sub.TN) drop between read data line 38 and node 44 when the stored bit has a high logical value, which becomes especially important during low-voltage operation. Inverter 18 can be removed by providing true and complementary read address signals, however this doubles the number of read address lines and requires significantly more surface area.
Thus, memory cell 10 suffers from speed limitations that become progressively worse as the power supply voltage decreases. As a result, memory cell 10 is not well-suited for low voltage, high speed operations, particularly with supply voltages on the order of 1.2 volts.
Low voltage operation is becoming increasing popular in a wide variety of applications. For instance, low voltage operation reduces power dissipation, which is critical for portable electronics such as laptop computers and cellular telephones with limited operating times between battery recharging. In addition, low voltage operation increases the reliability of integrated circuit chips. For instance, as MOS transistor dimensions are reduced, the electric field in the channel region near the drain tends to increase. If the electric field becomes strong enough, it can give rise to hot-carrier effects, in which electrons are injected into the gate insulator and change the threshold voltage of the device. Reducing the supply voltage reduces the electric field giving rise to hot-carrier effects.
Accordingly, a need exists for an application-specific SRAM memory cell that is well-suited for low voltage, high speed operation.